Study of N-type LTPS TFTs Degradation under Gate Pulse Stress in ON Region with Drain Bias

• Main Authors: Chang-Lung Chan, 詹長龍
• Other Authors: Ya-Hsiang Tai
• Format: Others
• Language: en_US
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/41836434076228847831

碩士 === 國立交通大學 === 電機學院光電顯示科技產業專班 === 96 === The purpose of this thesis is to study the degradation behavior of N-type poly-Si TFTs under AC operation. It differs from previous studies, the characteristics of poly-Si TFTs under gate pulse AC operation in the ON region with drain bias are investigated, which would be much similar to the real operation conditions in applications. Degradation of the device is examined for various conditions of AC gate pulse and DC drain bias. It is observed that the degradation is affected by the drain bias, pulse repetition number, gate pulse level, and duty ratio. On the basis of the comparison between the DC gate stress and AC gate stress both with large Vd, we proposed a new index VGO to estimate the equivalent DC Vg for the gate AC signal. It is further found from the results that the features of hot carrier effect and self-heating effect in DC stress are corresponding to gate AC stress with drain bias. In addition to this new finding, the relation between the device degradation and various duty ratios under AC operation with Vd is also evidenced. That is, hot carriers are the dominant cause of degradation under low-level of the gate voltage (Vgl), and the mobility degradation obviously increases with the decrease in duty ratio. However, the degradation is dominated by self-heating under high-level of the gate pulse (Vgh) and corresponding with the increase in duty ratio. Based on the similarity between the DC stress and AC gate stress, the reliability of poly-Si TFTs dynamically operated in the ON region could be simply estimated from its reliability behavior under DC stress conditions.