A Program-Erasable High-κ Hf3N2O5 Metal-Insulator-Silicon Capacitor

• Main Authors: Chun-Hsien Lin, 林俊賢
• Other Authors: Albert Chin
• Format: Others
• Language: en_US
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/6ned4b

碩士 === 國立交通大學 === 電機學院微電子奈米科技產業專班 === 96 === Memory cell capacitance is the crucial parameter which determines the sensing signal voltage, speed, data retention times, endurance and against the soft error event. However, the very large scale integration (VLSI) technology is continues down-scaling of the size of capacitors to reduce chip size and the cost. It will decrease dielectric thickness and result in the undesired leakage current. To solve this problem, the conventional silicon dioxide will be replaced with high dielectric constant (high-k) materials to increase the capacitance density and degrade the leakage current. Besides, capacitors also desire both good data retention and program-erasable capability for memory applications. In this study, we demonstrate a programmable-erasable MIS capacitor with a single high-k Hf3N2O5 dielectric layer for many applications such as volatile DRAM and non-volatile MONOS type memories. This device showed a capacitance density of ~ 6.5 fF/mm2, low program and erase voltages of +5 and -5 V, and a large Vth memory window of 1.5V. In addition the 25oC data retention was good, as in program and erase decay rates of only 2 and 6.2 mV/dec. In addition, we found a deep trapping level of 1.01~1.05 eV from measured J-V characteristics. The electrodes displayed a Schottky barrier height of 0.69~0.7 eV.