| Summary: | 碩士 === 國立交通大學 === 電子工程系所 === 96 === For today’s technology, uniaxial–process induced stress is used to improve device performance. One method is the adoption of the embedded and raised SiGe in the p-channel source and drain and a tensile capping layer on the n-channel device. The other method is with advantages of dual stress liners: compressive and tensile silicon nitride (SiN) for p- and n-channel devices, respectively. However, for further CMOS scaling, it is imperative to investigate other high mobility channel materials, such as Ge, strained Si/Ge and GaAs. Due to the complexity of the coupling valence band among the heavy, light and split-off bands, the treatment of one mass approximation applied to hole quantization in semiconductor inversion layer is incorrect. This thesis focuses on valence band calculations in various devices, such as Si MOS structure and double gate devices by iteratively solving the coupled Schrödinger and Poisson equations with six-band Luttinger-Kohn model. Finally, we developed a two-dimensional Monte Carlo simulation to study hole transport properties in SiGe and Ge quantum wells.
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