| Summary: | 碩士 === 國立交通大學 === 電子工程系所 === 96 === As the technology scales, it is well known that interconnect has become the dominant factor in determining the overall circuit performance and complexity. Buffer insertion is one of a very effective and useful techniques to improve the interconnect performance. The buffer insertion during floorplan stage usually clusters buffers in a region to minimize the area overhead, which may cause additional current and have the IR-drop violation. On the other hand, in complex digital system with relatively large die areas operating at very high frequencies, many global signals traveling across the chip need several clock cycles to reach their destinations, thus requiring the adoption of pipelined interconnects. We propose a methodology to pipeline interconnect during the floorplan stage and consider the IR-drop during the planning of buffers and flip-flops. The experimental results show our method can get a low system latency and without any IR-drop violation.
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