Simultaneous Buffer / Flip-Flop Station Planning and Voltage Drop Minimization in Floorplan Design
碩士 === 國立交通大學 === 電子工程系所 === 96 === As the technology scales, it is well known that interconnect has become the dominant factor in determining the overall circuit performance and complexity. Buffer insertion is one of a very effective and useful techniques to improve the interconnect performance. Th...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/zg4xe3 |