Clock and Data Recovery for Spread Spectrum Clock using Multiple Alternating Edge Sampling
碩士 === 國立交通大學 === 電子工程系所 === 96 === In this thesis, we propose a CDR circuit that operates at 6Gbps and conform to specifications of SATA generation three. This design incorporates dual-loop, the frequency synthesize loop and clock/data recovery loop are independent from each other, making this CDR...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/2czcm6 |