Low Power and Low Test Data Volume Testing for Scan Design VLSI

• Main Authors: Shih Ping Lin, 林世平
• Other Authors: Chung-Len Lee
• Format: Others
• Language: en_US
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/34128200432160268605

博士 === 國立交通大學 === 電子工程系所 === 96 === Scan design is now a necessary practice for today’s ICs when considering their testing. As the size of today’s ICs now becomes tremendously large, the traditional scan test becomes inefficient and troublesome due to two problems: the large test data volume which leads to unaffordable test application time and the high test power which may cause reliability problem to ICs. This dissertation makes a comprehensive study on these two test challenges. We propose several solutions. First, we proposes a scan test architecture like matrix where a new scan cell is invented to be bypassed during pattern shifting when it is not addressed. This reduces the number of transitions of scan cells and the circuit under test (CUT) hence reduces the power consumption. In addition, the scan cell does not introduce any penalty on degrading the performance of the CUT. Moreover, we also adopt a design to reduce the power of clock tree. Experimental results show that it can achieve nearly 99% power savings for large size designs. Next, based on Random Access Scan (RAS), we propose a cocktail scan strategy. After surveying previous works, we present several improved strategies to improve the efficiency on test compression. These are: (1) a constrained static compaction, which is a compaction strategy to keep the number of bit flips the same after test cubes are compacted; (2) optimum reordering of test cubes: which is the best ordering of test cubes and is adopted by examining several cost models to estimate the number of bit flips; (3) test cube dropping: a method to drop test cubes while guarantee the same fault coverage. Experimental results show that the adoption of the above strategies is very effective in reducing the number of bit flips, leading to an 86% reduction in test data and ten times of speedup in test application time. Thirdly, we propose an encoding scheme, Adaptive Encoding, which is suitable for test data compression in System-on-Chip (SoC), by utilizing an embedded memory and encoder. The conventional test data encoding schemes usually suffer the drawback that the compression rate is affected by the block size, leading inefficiency in compressing test data. The proposed scheme supports variable block size encoding, thus eliminates the above drawback and improves the encoding efficiency. In addition, we also adopt a hybrid test technique to further reduce the volume of test data. We also try to make consideration of making tradeoff between the test compression rate and the test power during the above process. Experimental results show that the proposed method effectively reduces the volume of test data and test power. More specifically, we can reduce the test energy by 91.60% and reduce the peak power by 15.57% at the expense of 10.82% loss in test compression. Finally, we propose a Multilayer Data Copy (MDC) scheme, which is very suitable for designs with large number of scan chains, to obtain high test compression with low-power testing. This scheme proposes an architecture which performs two operations, Copy and Shift, to achieve high test compression rate by exploiting don’t care bits of test patterns. MDC can not only be used to compress test data sets but also be incorporated into automatic test pattern generator (ATPG) to give better efficiency. Similarly, we also consider test power reduction when do test data compression. Systematic study on this scheme shows that the schem has high compression rate and low testing power but has a negligible area overhead.