Low Power and Low Test Data Volume Testing for Scan Design VLSI
博士 === 國立交通大學 === 電子工程系所 === 96 === Scan design is now a necessary practice for today’s ICs when considering their testing. As the size of today’s ICs now becomes tremendously large, the traditional scan test becomes inefficient and troublesome due to two problems: the large test data volume which l...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2007
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/34128200432160268605 |