| Summary: | 博士 === 國立交通大學 === 電子工程系所 === 96 === In this dissertation, three approaches to incorporating nitrogen in CoTiO3 high-�� dielectric films, including the ion implantation of N2+, ion implantation of N+, and N2O plasma treatment, have been investigated. Nitrogen incorporation by ion implantation of N2+ can improve the electrical properties in terms of gate leakage, breakdown voltage and time-to-breakdown (TBD). To reduce the impinging mass of implanted ion species, N+ ion implantation has been used. The same trends can be found as those produced using N2+. A N2O plasma treatment is also an excellent method to improve the electrical properties, exhibiting better-behaved C-V curves, lower gate leakage currents and higher breakdown voltages.
Two silanol precursors, tert-butyldimethyl silanol (BDMS) and tris(tert-pentoxy) silanol (TPOS), are evaluated as silicon precursors for hafnium silicate deposition with tetrakis-(diethylamido) hafnium (TDEAH). BDMS has one OH group, which should react with chemisorbed TDEAH. However, the other t-butyl and methyl groups can passivate the substrate surface, and stop the further absorption of TDEAH. Carbon-free hafnium silicate thin-films are deposited by MOCVD using alternative pulses of TDEAH and TPOS precursors. Hafnium silicates with high silicon contents (Hf1-xSixO2, x >0.5) are deposited at 250 �aC without additional oxidants. MOS capacitors are fabricated for electrical characterizations. A forming gas anneal can improve the hafnium silicate interface quality. This low-temperature process could be promising for TFT or optoelectronic applications.
Hemispherical Si nanocrystals are self-assembled using an in-situ thermal agglomeration technique. Ultrathin (0.9–3.5 nm) a-Si films are deposited on a 4-nm tunnel-oxide layer using electron-beam evaporation. An in-situ annealing can then activate the thermal agglomeration of Si and transform the ultrathin a-Si films into Si nanocrystals. The Si agglomeration process is evaluated with various processing parameters such as annealing temperatures, surface oxide conditions, and initial Si film thickness. Also, it is demonstrated that XPS measurements can effectively provide the information of the nanocrystal agglomeration. Calculations are made based on the photoelectron attenuation theories, and a simple model is proposed. Comparisons between the calculated results and the experimental data have shown a fairly good match.
The fabrication of a Si nanocrystal-embedded nonvolatile memory has been demonstrated using a thermal agglomeration technique. MOS capacitors and MOSFETs embedded with hemispherical Si nanocrystals are fabricated and characterized. A stored charge density of 4.1�e1012 cm-2 (electron + hole) is obtained with a highest nanocrystal density of 3.9�e1011 cm-2. Uniform FN tunneling is used to program and erase the Si nanocrystal floating-gate n-MOSFETs. A Vt window of 0.9 V is achieved under P/E voltages of �b10 V for 0.02/0.1 s. The memory device also shows good endurance and charge retention behaviors after 10000 P/E cycles. Increasing P/E voltages to �b15 V creates a large memory window (>2.7 V) with the proposed memory device. After a retention test for 100 hours, a memory window of 1 V is maintained. The retention characteristics have shown little temperature dependence with the Si nanocrystal memories, indicating that the charge-loss process is determined by the direct tunneling from nanocrystals into the oxide/Si-substrate interface states.
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