LOW-LEAKAGE POWER-RAIL ESD CLAMP CIRCUIT IN NANOSCALE CMOS TECHNOLOGY
碩士 === 國立交通大學 === 電機學院IC設計產業專班 === 96 === The aim in this thesis is to design the low-leakage power-rail ESD clamp in nanoscale CMOS technology. The principles are using circuit and component characteristics to minimize leakage of the circuit. Besides having the lowest leakage current, it also can h...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/66617011935518793997 |