| Summary: | 碩士 === 國立成功大學 === 工程科學系專班 === 96 === In the integrated circuit manufacturing process, Patterns of small sizes often needs to be formed on the wafer. The method of pattern formation is to use developers to remove the exposure photo resist so that pattern can be directly transferred to wafer. Etching method is the technology used, including isotropic etching and non-isotropic etching. The contact plasma etching process is a non-isotropic etching. As the process pattern dimension shrinks gradually, it is important to know how to control the contact line width effectively and fast.
In this study, the change of bottom antireflective coating etching recipe parameter to adjust the contact line width is the main focus. Comparing parameter change along with the contact line width, three factors are considered, namely differences of C4F8 flow, process time, and process pressure. Furthermore, the correlation between contact line width and wafer electrical test result is also analyzed.
According to the experiment results, firstly increasing the C4F8 gas flow by 1 sccm from 12sccm, decreases the line width approximately 1.14nm (~1.6%); Secondly, increasing process time by 6 seconds from 120seconds, decreases the line width approximately 0.76nm(~1.06%); Lastly, increasing the process pressure by 10mTorr from 130mTorr, decreases the line width approximately 0.34nm(~0.47%).Decreasing the contact line width by 1nm will cause wafer electrical test contact resistance to increase by0.76Ω
From the results above, it can be concluded that C4F8 gas flow and process time is the key factor for line width regulation, then the process finally by the pressure. The smaller line width is higher electrical test resistance presents.
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