Design of small Chip-Area Balun in CMOS Technology
碩士 === 國立中興大學 === 電機工程學系所 === 96 === This thesis includes five topics. Firstly, the stacked Balun structure will be addressed. The measurement shows that the stacked Balun structure not only improvements the coupling coefficient with 58% but also saves layout area with 80% comparing with planar stru...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/90283879860751290424 |