| Summary: | 博士 === 國立中興大學 === 資訊科學與工程學系 === 96 === In this dissertation, we discuss the scan-based test architectures that can be used for test volume and time reduction in SOC or digital circuits. Our approaches can be used in single or multiple scan chain architecture. We also proposed the layout aware scan chain reordering constrain to limit the scan cell reordering range. It can limit the wire length too long that compared with unlimited scan cell reordering range.
In the content, we first discuss the continuous scan architecture that based on test per clock approach for scan-based design, in which a test is conducted in every clock cycle. Conventional scan-based designs take a lot of test time in shifting test patterns and output responses, which greatly increases the testing cost. With the recent development in output response compression, it is possible to observe test output on a cycle-by-cycle basis. The contribution of this approach is significantly reduces the test time when appropriate test vectors are selected. We developed algorithms to generate and compact test inputs vectors under the proposed test environment. A further reduction in test time can be achieved by concurrent test of multiple modules. Experimental results on ISCAS’85 and ISCAS’89 benchmark circuits show that the proposed method achieves high fault coverage with significantly reduced test data volume and shorter test application time. On the average, it requires only about 18% to 28% of the clock cycles required for the best-known test set applied to conventional scan-based design. No extra hardware is required if output compression techniques have already been included.
Second, we discuss a test data compression scheme targeted for minimizing the amount of test data. The proposed scheme can reduce the test application time and minimize the amount of compressed test data, which reduces the size of data memory in ATE and the time needed to transfer test data. A decoder design is also presented. Experimental results on ISCAS benchmark circuits show that the compressed data produced by our method are much smaller than previous methods.
Subsequently, we discuss the broadcast-based test compression techniques. It can reduce both test data and test time. However, the success of such methods heavily depends on the percentage of test patterns that can be broadcasted. We first conduct a
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quantitative analysis that shows the simple broadcast architecture cannot achieve good test time/data compression even under a test set with very high level of don’t care bits. Multi-mode segmented scan test architecture (MSSA) is then presented to solve the problem of low broadcast rate. Three operation modes are supported in this architecture: broadcast, multicast, and serial. In MSSA, efficient test data compression is achievable with limited hardware overhead, as serial-mode operations are largely eliminated. An efficient algorithm for the two-way partitions of the scan segments is proposed to construct multicast mode configurations. Finally, we present a layout-aware scan chain ordering method to further improve test compression. The problem of ordering scan cells in multiple scan chains is mapped to a constrained standard cell placement problem in physical synthesis, and the simulated annealing method is used to solve the problem. The routing lengths of the scan chains are also taken into account in the ordering process. Experimental results show that the method is both efficient and effective. It achieves better results than all previously known compression methods.
Finally, Launch-off-Shift (LOS) is a widely used technique for delay test in scan-based design. Test data compression for LOS patterns, however, is less efficient. We first analyze the reason for low compression rate in LOS patterns, and present an LOS test enabled scan architecture that supports three operation modes: broadcast, multicast, and serial. Efficient LOS test data compression can be achieved under this architecture with limited hardware overhead. An ATPG method for LOS test patterns under the proposed architecture is also presented. Experimental results show that most of the serial scan operations can be replaced by multicast operations, and thus achieve much better compression rate.
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