Test Reduction for SOC with Scan-Based Method
博士 === 國立中興大學 === 資訊科學與工程學系 === 96 === In this dissertation, we discuss the scan-based test architectures that can be used for test volume and time reduction in SOC or digital circuits. Our approaches can be used in single or multiple scan chain architecture. We also proposed the layout aware scan c...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2008
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/88340055779364553462 |