A Synchronous Modular Multiplier with Variable Latency Design
碩士 === 輔仁大學 === 電子工程學系 === 96 === Modular multiplication is a very important arithmetic operation in cryptography systems and residue-based computation. This paper presents a synchronous modular multiplier that has variable computation latency depending on operand values. The modular reduction opera...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2008
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/63248887794416589784 |