Two-Layer Floorplanning Based on Sequence-Pair Representation
碩士 === 大葉大學 === 電機工程學系 === 96 === Floorplanning is a very important step of physical design in the backend of IC design. Generally, one layer floorplanning problem is to solve the problem of placement on 2D plane. However, as system chip becomes more complex, System-On-a-Chip (SoC) becomes growing u...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/21694724365654776540 |