Implementation of an Interleaver for Turbo Codes Using the MIPS-like Architecture
碩士 === 大葉大學 === 電機工程學系 === 96 === The turbo codes are wildly applied in most leading technology of wireless communication. Therefore, this study develops a 32-bit RISC (Reduced Instruction Set Computer) microprocessor with the MIPS-like architecture embedded an interleaver for turbo codes by using t...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/66169787067498665704 |