Current-Cell Matrix Digital to Analog Converter
碩士 === 中華技術學院 === 電子工程研究所碩士班 === 96 === This thesis proposes a new matrix digital to analog converter. All the results are simulated by TSMC 0.18m CMOS technology. The INL and DNL are 0.26 and 0.25 LSB for the 4 bit DAC, respectively. The INL and DNL are 0.23 and 0.25 LSB for the 8 bit DAC, respect...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2007
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/27655992063157976458 |
| Summary: | 碩士 === 中華技術學院 === 電子工程研究所碩士班 === 96 === This thesis proposes a new matrix digital to analog converter. All the results are simulated by TSMC 0.18m CMOS technology. The INL and DNL are 0.26 and 0.25 LSB for the 4 bit DAC, respectively. The INL and DNL are 0.23 and 0.25 LSB for the 8 bit DAC, respectively. The power consumption of 8-bit DAC is about 8.9mW.
The proposed DAC also has advantages of simple encoder circuit to control current sources. It will decrease the size of circuit area.
The DAC can also expand to more bit in the unit of 4 bits, for example, 8, 12 etc. It could be competitive with conventional matrix DAC.
|
|---|