Frequency Multiplier Based on DLL Technique
碩士 === 長庚大學 === 電子工程學研究所 === 96 === By the advantages of stable and easy to design, DLL has been widely used in high-speed clock generator or clock deskew. Frequency multiplier based on delay-locked loop (DLL) is proposed in this thesis. The frequency multiplier is realized by using the multiple clo...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Published: |
2008
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/39268905404549832556 |