Design and Implementation of Diode-Clamped Three-Level Inverters with Neutral-Point Voltage Balance
碩士 === 國立臺北科技大學 === 電力電子產業研發碩士專班 === 95 === The purpose of this thesis is to design and realize a diode-clamped three-level inverter with neutral-point voltage balance. The harmonic contents of output voltage of three-level inverters are less than those for two-level inverters. However, diode-clampe...
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| Format: | Others |
| Language: | zh-TW |
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2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/566u35 |
| Summary: | 碩士 === 國立臺北科技大學 === 電力電子產業研發碩士專班 === 95 === The purpose of this thesis is to design and realize a diode-clamped three-level inverter with neutral-point voltage balance. The harmonic contents of output voltage of three-level inverters are less than those for two-level inverters. However, diode-clamped three-level inverter has the problem of neutral point voltage balance. This thesis uses two control methods to balance the voltage of DC-link capacitors and reduce the total harmonic distortion of output waveforms.
The simulation results are derived from Matlab®/Simulink® software. The experimental results are derived from an induction motor drive controlled by digital signal processor. It will be shown that the simulation results and experimental results confirm the performance of the control methods for neutral point voltage balance in diode-clamped three-level inverters.
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