Design and Implementation of Diode-Clamped Three-Level Inverters with Neutral-Point Voltage Balance
碩士 === 國立臺北科技大學 === 電力電子產業研發碩士專班 === 95 === The purpose of this thesis is to design and realize a diode-clamped three-level inverter with neutral-point voltage balance. The harmonic contents of output voltage of three-level inverters are less than those for two-level inverters. However, diode-clampe...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/566u35 |