Duty Cycle Corrector Based on Pulse Shrinking/Stretching Mechanism
碩士 === 國立臺灣科技大學 === 電子工程系 === 95 === The duty cycle correctors (DCCs) are widely used to adjust the clock duty cycle to 50% for DDR (double data rate)-SDRAM, double-sampling ADC, DLL (delay locked loop) and PLL (phase locked loop), where both clock rising and falling edges are used for operation. Th...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/64732985219389742835 |