HW/SW Interface Synthesis for SoC Design
碩士 === 臺灣大學 === 電機工程學研究所 === 95 === In SoC design, HW/SW interface design is error-prone. Different OS and bus system provide different HW/SW interface. Different IPs have different speed, data rate, throughput. Integrating them into a SoC system by hands is time-consuming and error-prone. We propos...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/37862480239813080235 |