A System Design Methodology for Concurrency from UML to SystemC
碩士 === 國立臺灣大學 === 電機工程學研究所 === 95 === Increasing demands for more performance have taken the system designs based on VLSI chips to their limits. The design bottleneck now is the interconnect delays and power consumptions rather than the basic gate delays. One way to eliminate the latency and power c...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/92220894024871844698 |