Design and Implementation of 3.125Gb/s Clock and Data Recovery Circuit Using Delay-Chain Frequency Detector
碩士 === 國立臺灣大學 === 電子工程學研究所 === 95 === A clock and data recovery circuit plays an important role in wireline communication systems. It serves to recover the data with jitters and noises passed through long-distance transmission. The implementation is usually achieved by a phase-locked loop (PLL), and...
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| Format: | Others |
| Language: | en_US |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/50060301845618281204 |