Low Power Mapping of Cores onto Hybrid Noc Architectures
碩士 === 臺灣大學 === 資訊工程學研究所 === 95 === With the advance of the semiconductor technology, a huge number of transistors available on a single chip allows designers to integrate tens of intellectual property (IP) blocks together with large amounts of embedded memory. In tradition, data was transferred wit...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/25427377363483077617 |