The Study of CMOS Shallow Trench Isolation Step-height for Device Characteristics

• Main Authors: Ying-Tsung Chen, 陳盈淙
• Other Authors: Keh-Chyang Leou
• Format: Others
• Language: zh-TW
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/37622253468231688097

碩士 === 國立清華大學 === 工程與系統科學系 === 95 === This research studies the effect on device performance from the step-height difference between Shallow Trench Isolation (STI) and its neighboring transistor active-region in Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The study utilizes the two methods of Chemical Mechanical Planarization (CMP) and Hydro-Fluoric Acid (HF) wet etch to create dielectric step-height difference higher or lower than standard, than discuss the effect on transistor isolation properties, specifically Junction Leakage and it’s effect on device performance, including Short Channel Effect (SCE), Narrow Width Effect (NWE), etc. For qualitative analysis, it was discovered that the final STI physical structure is determined by the initial step-height right after CMP or HF wet-dip process is finished. It is gradually decrease correlations both step-height and divot. On quantitative analysis, we find out the relationship of specific pattern thickness versus the outcome of step-height. The relationship of CMP Nitride thickness and step-height was found to be 0.43：1; HF wet-dip oxide thickness and step-height’s relationship was found to be 1.77：1. In electrical performance, the results show that when step-height was reduced from 660 Å to 170Å, 3 to 5 order of magnitude difference in Inter-well leakage was found in the minimum feature transistor (clearance 0.08 �慆). For NWE property, there was a 10 to 20% enhanced in saturation drain current (Idsat) for the narrowest width device (0.12 �慆). For SCE property, 9.8 to 16.5 mV/V difference on DIBL was found for the shortest tunnel-length device (50 nm). It is shown that transistor performance can be significantly affected by step-height change. Besides, we employed 3 patterns of difference sizes, attempting to find the individual contribution of perimeter and area on interface leakage. The results show that area’s contribution to leakage is 22 to 24 times as much as perimeter’s contribution, indicating the device size as the determining factor for device leakage. We can make use of this relationship to calculate the leakage value for patterns with known area and perimeter; for step-height between 660 to 390 Å, the error margin is within 10%. This study links the relationship of the process thickness parameter between step-height and electrical performance; the result can help control device abnormality, furthermore can be the development basis for Advanced Process Control, thus be used as an important reference for process control and yield improvement.