Novel Nanowire SONOS TFTs Functioned as Nonvolatile Memory and Transistor

• Main Authors: Shih-Ching Chen, 陳世青
• Other Authors: Chen-Hsin Lien
• Format: Others
• Language: zh-TW
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/94449017372591563788

博士 === 國立清華大學 === 電子工程研究所 === 95 === In first part, presents a method to enhance the performance of polycrystalline silicon thin film transistors (ploy-Si TFTs) by using an oxide-nitride-oxide (ONO) gate dielectric and the multiple nanowire channels structure. Experimental results indicate that the performance of the device was enhanced by using the ONO multilayer, because the ONO gate dielectric constant is increased compared to the conventional oxide gate dielectric. Additionally, the TFTs with a ten nanowire channel structure (NW-TFTs) have superior electrical characteristics than other TFTs. Since the crowding of the gate fringing field at the narrow channel surface of nanowire causes the large electrical field, the devices with nanowire structure have the better gate control ability. Hence, the device characteristics of SONOS-TFT with NW structure are mainly improved by the high electrical field originated from fringing electrical field effect. Furthermore, the SONOS-TFT also can be functioned as a nonvolatile memory under adequate bias operation. The proposed NW SONOS-TFT can exhibit high program/erase (P/E) efficiency due to the good gate control ability originated from fringing electrical field effects. Next, as the thickness of ONO layer thinner than that of poly-Si channel, the SONOS-TFT with nanowire channels is surrounded by poly-gate. The experimental results show that the NW SONOS-TFT has the superior electrical characteristics due to the tri-gate structure and additional corner current induced by corner effect. The simulation of electrical field results verified that the enhancement of P/E efficiency in NW SONOS-TFT is mainly attributed to the large number of corners and their corner effect. Also, the simulation result on electrical field reveals that the electrical field across the tunnel oxide is enhanced and that across the blocking oxide is reduced at the corner regions. This will lead the parasitic gate injection activity and the erasing speed can be apparently improved in the memory device, due to the pronounced corner effect and narrow channel width. In addition, the good endurance and retention are also obtained in this device. Finally, we apply the pi-gate structure on nanowire channel for polycrystalline silicon thin-film transistor (poly-SiTFT) combined with nonvolatile silicon-oxide-nitride-oxide-silicon (SONOS) memory. The proposed pi-gate TFT-SONOS has superior electrical characteristics of transistor, such as smaller threshold voltage (Vth) and steeper subthreshold slope (SS). The output characteristic also exhibits the high driving current and suppression of the kink-effect. For memory application, the device can provide high program/erase (P/E) efficiency and large threshold voltage shift under adequate bias operation. The enhanced performance for pi-gate SONOS-TFT is attributed to the larger effective channel width and number of corners.