Cell-based & Modulized Nanometer Interconnect Test Structure Generator for BEoL

• Main Authors: Ming-Huei Tsai, 蔡明輝
• Other Authors: Keh-Jeng Chang
• Format: Others
• Language: zh-TW
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/24054100523068758060

碩士 === 國立清華大學 === 資訊工程學系 === 95 === In the semiconductor industry, test structures are the important method used to observe the parameters’ variation scope of new process, and establish process corner model. When the VLSI manufacturing technology develops from micro-Al to nanometer-Cu process, many problems which are secondary effects or never encounter before, such as the interconnect challenges, chemical property of copper, low-k material, CMP and the gap between sub-wavelength and silicon feature size……etc, now unceasingly occur. These new defects in particular need more special test structures in order to achieve the process simulation and monitor. Realizing the advantage of automation, industry nowadays tends to use computer software to massively generate all kinds of correct test structures. This efficient way will reduce conventional test chip development cycle, which is a person-months high cost but low reliability task. In this paper, the automatic interconnect test structure generator is our key point. We’ll aim at Test-Gen by Hung-Chih Li to make the improvement. We not only add the knowledge of CMP effect, lithography constraint and the concept of cell library but provide the modulized architecture in the new automatic program so that users can generate each kind of test structure by their requirements. Besides, we propose a new 4-terminal comb test structure for capacitance measurement, which can decouple the process effects and verify the electrical properties of the test structure itself or the measurement machine. Users can instance the new structure in our build-in friendly template library. The overall flow from specification of different splits to final GDSII layout consumes little time, and can adjust fast along with the advance process. It’s helpful to accelerate the corner model development of the BEoL.