Test and Analysis of VLSI Interconnect systems
博士 === 國立中央大學 === 電機工程研究所 === 95 === This thesis is a comprehensive works of interconnect models in VLSI system. The relative works are suitable to explore the influence of interconnect models on high-speed digital signal. For basic models, the wired-logic is used to propose an efficient interconnec...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/34638520387274416684 |