Study of N-type Poly-Si TFTs Degradation Under Gate Pulse Stress in Off Region with Drain Bias

• Main Authors: Wei-Lun Shih, 施偉倫
• Other Authors: Ya-Hsiang Tai
• Format: Others
• Language: en_US
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/00388523289196745631

碩士 === 國立交通大學 === 顯示科技研究所 === 95 === Polycrystalline silicon (poly-Si) thin film transistors (TFTs) have recently attracted much attention in the application on the integrated peripheral circuits of active matrix liquid crystal displays (AMLCDs) and active matrix organic light emitting diode (AMOLED) displays. The significant advantages over amorphous silicon (a-Si) TFTs are in the higher current driving capability and the better reliability. In poly-Si TFT-controlled displays, poly-Si TFTs are used to implement pixel circuits and driving circuits on a single glass substrate to reduce system cost and posses compact module. Therefore, the poly-Si TFT is the best candidate to realize system–on–panel (SOP). However, unlike pixel TFTs, TFTs in driver circuits are subjected to high-frequency voltage pulses. Therefore, the degradation mechanism under dynamic operation should be understood in detail. In this thesis, the device degradation of low-temperature polycrystalline thin film transistor under gate AC stress in off region with drain bias has been investigated. The effective drain current, pumped by the AC gate voltages in the off region, undergoes different electric field effects near the source and drain junction and therefore results in different degradation behavior near these two regions. It is noticed that the degradation depends profoundly on the DC drain bias. It is also affected by the rising time Tr, falling time Tf, and the Vg range. This finding would be helpful in the understanding and evaluation of the device degradation mechanism and provide a guideline to design for reliability of poly-Si TFT circuit.