Low-Voltage Low-Power 5-GHz Receiver Front-End Circuit Design for Wireless Sensor Networks
碩士 === 國立交通大學 === 電子工程系所 === 95 === This thesis aims at design of a low-voltage low-power receiver front-end circuit applicable to wireless sensor networks. Two chips are realized. In the first chip, a low-power double-balanced mixer is designed in a folded topology. A transconductance stage with ph...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/13482087189832994108 |