On the Study of Design Optimization for Network-on-Chip Platform
博士 === 國立交通大學 === 電子工程系所 === 95 === As System-on-Chip (SoC) designs progressively grow, reducing the development time becomes a crucial challenge. Therefore, the Network-on-Chip (NoC) generator, the FFT generator, and the multiplier generator are developed for reducing the design time. In this work...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/93517538963876444621 |