Ultra Low Power Area Efficient All Digital Phase-Locked Loop Frequency Synthesizer
碩士 === 國立交通大學 === 電子工程系所 === 95 === A new all digital phase-locked loop (ADPLL) architecture with low power algorithm is presented in this thesis. The proposed low power search algorithm can accomplish phase lock process within 22 input clock cycles and make the hardware simple, area small. In thesi...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/84333963129857541619 |