VLSI Design of Register Array Based Fast Fourier Transform Processor

• Main Authors: Ming-Che Chang, 張銘哲
• Other Authors: Gin-Der Wu
• Format: Others
• Language: en_US
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/48202659275134945378

碩士 === 國立暨南國際大學 === 電機工程學系 === 95 === This paper proposed the chip design of speech recognition for multimedia system. It is composed by three cores: a register array based fast Fourier transform (FFT) processor, a Mel-scale frequency cepstral coefficient (MFCC) circuit, and a dual-ALU digital signal process (DSP) processor with dynamic time warping speech recognition algorithm. The DSP processor and MFCC processor had been implemented by previous researcher. In this FFT processor, we proposed a novel register array based pipelined radix-22 structure to reduce power consumption and computation cycles. The chips are synthesized by TSMC 0.18um cell library. The gate count of the FFT chip is about 196172. The latency is about 2.56μs. The FFT chip is work at 100 MHz.