VLSI Design of Register Array Based Fast Fourier Transform Processor
碩士 === 國立暨南國際大學 === 電機工程學系 === 95 === This paper proposed the chip design of speech recognition for multimedia system. It is composed by three cores: a register array based fast Fourier transform (FFT) processor, a Mel-scale frequency cepstral coefficient (MFCC) circuit, and a dual-ALU digital signa...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/48202659275134945378 |