An 8-bit 500MS/s Flash ADC Using Capacitor Averaging with a Single-Phase Clock
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 95 === Averaging networks suppress the random offset efficiently between the comparators in flash ADCs, but it causes limitations at the averaging network boundaries. Although the effect can be resolved by additional terminal circuits, it costs larger power consumpti...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/65922434975377095292 |