Using MTS and Neural Network for WAT and Circuit Probe yield model in Semiconductor Process.
碩士 === 明志科技大學 === 工業管理研究所 === 96 === Wafer yield is important key index of financial affairs, process capability and even guarantee the products could be supplied steadily. Under present control parameter and method adopted, appear some wafers yield on the low side, even zero.With the hiving off of...
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ndltd-TW-095MIT000410062015-11-30T04:02:17Z http://ndltd.ncl.edu.tw/handle/62549901535087578970 Using MTS and Neural Network for WAT and Circuit Probe yield model in Semiconductor Process. 整合馬氏田口系統與類神經網路於晶圓允收測試與晶圓針測良率模型之研究 Bing-De Wu 吳秉德 碩士 明志科技大學 工業管理研究所 96 Wafer yield is important key index of financial affairs, process capability and even guarantee the products could be supplied steadily. Under present control parameter and method adopted, appear some wafers yield on the low side, even zero.With the hiving off of yield, it influences different yield parameter groups that lead under the situation to use wafer acceptance test(WAT)data to find out. Carry on different improvement activities to different yield, use the parameter group to predicting the Circuit Probe yields model. Based on WAT datas, Mahalanobis-Taguchi System(MTS)need not any assumption and non-equilibrium categorised ability of data is it look for different yield parameter groups. And using neural networks to predicting Circuit Probe yield model. Pass factory afford the real data to analyse and prove. In accordance with dividing the yield into five groups under the engineer's suggestion at first. Using MTS to finding influence important parameter in different yield groups, it classifies total accuracy is reaching 0.7822~0.8997. MTS can gain rank of value through key parameter, to gain value heavy parameter is it carry on improving in order to improve yield to have priority. Building constructing in yield model. MTS parameter group make up as input parameter, neural network of using Group Method of Data Handing(GMDH)set up predict yield model as best. The reaching 0.6012 of the model. Chien-Chih Wang 王建智 2008 學位論文 ; thesis 85 zh-TW |
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碩士 === 明志科技大學 === 工業管理研究所 === 96 === Wafer yield is important key index of financial affairs, process capability and even guarantee the products could be supplied steadily. Under present control parameter and method adopted, appear some wafers yield on the low side, even zero.With the hiving off of yield, it influences different yield parameter groups that lead under the situation to use wafer acceptance test(WAT)data to find out. Carry on different improvement activities to different yield, use the parameter group to predicting the Circuit Probe yields model.
Based on WAT datas, Mahalanobis-Taguchi System(MTS)need not any assumption and non-equilibrium categorised ability of data is it look for different yield parameter groups. And using neural networks to predicting Circuit Probe yield model.
Pass factory afford the real data to analyse and prove. In accordance with dividing the yield into five groups under the engineer's suggestion at first. Using MTS to finding influence important parameter in different yield groups, it classifies total accuracy is reaching 0.7822~0.8997. MTS can gain rank of value through key parameter, to gain value heavy parameter is it carry on improving in order to improve yield to have priority. Building constructing in yield model. MTS parameter group make up as input parameter, neural network of using Group Method of Data Handing(GMDH)set up predict yield model as best. The reaching 0.6012 of the model.
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Chien-Chih Wang |
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Chien-Chih Wang Bing-De Wu 吳秉德 |
author |
Bing-De Wu 吳秉德 |
spellingShingle |
Bing-De Wu 吳秉德 Using MTS and Neural Network for WAT and Circuit Probe yield model in Semiconductor Process. |
author_sort |
Bing-De Wu |
title |
Using MTS and Neural Network for WAT and Circuit Probe yield model in Semiconductor Process. |
title_short |
Using MTS and Neural Network for WAT and Circuit Probe yield model in Semiconductor Process. |
title_full |
Using MTS and Neural Network for WAT and Circuit Probe yield model in Semiconductor Process. |
title_fullStr |
Using MTS and Neural Network for WAT and Circuit Probe yield model in Semiconductor Process. |
title_full_unstemmed |
Using MTS and Neural Network for WAT and Circuit Probe yield model in Semiconductor Process. |
title_sort |
using mts and neural network for wat and circuit probe yield model in semiconductor process. |
publishDate |
2008 |
url |
http://ndltd.ncl.edu.tw/handle/62549901535087578970 |
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