Modeling of Wafer Die Yield by WAT Parameters

• Main Authors: Chen-Yu Wang, 王振宇
• Other Authors: Kuen-Tai Cheng
• Format: Others
• Language: zh-TW
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/19801027159515533428

碩士 === 明志科技大學 === 工業管理研究所 === 95 === Wafer die yield is a key index of business profit at the semiconductor industry as the development of the semiconductor production technology and wafer size increases. Thus, the wafer die yield prediction models become a very important issue to this industry. Early researches mostly use such parameters as defects on wafer and wafer size cooperate with a regular distribution, such as Poisson distribution or Negative Binomial distribution, to establish the wafer die yield prediction model. Since Stapper proposed the fault clusters cause by randomly and system factors on 1989 [23] [24], cluster indexes are combined to fix yield models to increase prediction accuracy. However, these prediction methods of yield models might not be suitable and accurate for all semiconductor manufacturers. In this study, we try to find out the connection between the wafer acceptance test (WAT) data and circuit probe yield. A simple, efficient and accurate wafer die yield prediction model with less WAT parameters is proposed. Various Neural Network analysis techniques such as Backpropagation Neural Network (BPNN), General Regression Neural Network (GRNN) and Group Method of Data Handling (GMDH) are analyzed and compared. Result of this research shows Backpropagation Neural Network in selecting WAT parameters is valid and efficient. The GMDH is recommended for establishing the model, because of the following advantages: less variables used, ability to catch data pattern, and accuracy.