| Summary: | 碩士 === 義守大學 === 電子工程學系半導體暨封裝測試產業研發碩士 === 95 === This research is based on the premise to improve the product test in current testing house.The basic test theory including DC test, functional test, AC test and test equipment is described in detail in this work. Furthermore, a brief introduction of the memory test equipment such as FT or CP tester and FT hanlder or CP prober is given. The memory test flow for mass production is provided to have a more complete view for memory test in testing house. The applications of the memory test algorithms such as march algorithm are discussed.
A memory test program revision experimental work is carried on to study the test yield problem which is very important for the testing house profit. The memory test analysis will be used for speed binning experiments. The experimental results can provide customers to evaluate the efficiency of the program revision. The improvements including yield promotion, test time reduction, and cost down. In the experiment, the test results indicate the test time reduction can be achieved and maintain fault coverage and test yield at FT2(85℃). The improvement in fault coverage and 2% test yield increase can be achieved under a little bit longer test time at FT3(-10℃). The reach results of this dissertation are successfully run in 10 engineering lots and adopted for mass production.
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