Low-Power Built-in Self-Test Techniques for Embedded SRAMs
碩士 === 輔仁大學 === 電子工程學系 === 95 === The severity of power consumption during parallel BIST of embedded memory cores is growing significantly. In order to alleviate this problem, an address sequence reordering technique and a row bank-based pre-charge technique are proposed for low-power testing of emb...
Main Authors: | , |
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Other Authors: | |
Format: | Others |
Language: | en_US |
Published: |
2007
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Online Access: | http://ndltd.ncl.edu.tw/handle/55675209099184789244 |