Efficient BIST Techniques for Wavefront Array Processor for Motion Estimation and Compensation in the Transform Domain
碩士 === 輔仁大學 === 電子工程學系 === 95 === Testable design techniques for a systolic motion estimator based on C-testability and M-testablility conditions are proposed in this paper. The systolic array in motion estimator can be viewed as a two-dimensional iterative logic array (ILA) which is composed of pro...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/94277165106399813270 |