| Summary: | 碩士 === 中華大學 === 資訊工程學系(所) === 95 === In VDSM technologies, the process variation becomes more and more serious. Due to the difficulty of lithography and manufacture in nanometer process, the concept of yield-driven design becomes more and more important for modern chip designs. For a given design, the design flow may focus on the yield impact on three physical factors: wires, vias and cells. To reduce the yield loss due to via failure and wire short and open failures is a very important issue in DFM. In this paper, the yield model to analysis yield on a chip is firstly proposed to model the via、wire yield in post detail routing. Given a particle defect size and the width constraint of any wire segment in the RST, all the paths in the routing nets are reconstructed and the widths of all the wire segments are reassigned to minimize total routing area of the RST and satisfy all the width and timing constrained for critical area minimization by running a timing-constrained wire sizing process. A two-phase insertion approach for yield optimization is proposed to insert on-track redundant vias by finding a maximum matching result in a bipartite graph and insert off-track redundant vias by using a maximum constrained edge-pair matching result in a multi-partite graph with via sharing constraints. According to the Poisson yield model for redundant via insertion, wire sizing and path reconstruction, the experimental results show that our proposed timing-constrained path reconstruction for critical area minimization (TYPR), timing and weight-constrained wire sizing for critical area minimization (TYWS) and yield-driven two-phase redundant via insertion (YRVI) approach can improve 5.5%~44.8% chip yield for the tested benchmarks.
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