| Summary: | 碩士 === 長庚大學 === 電子工程研究所 === 95 === In more recent years, various mobility-improvement technologies using process-induced local stress of devices have been evolved as a potential candidate for high speed and low power logic CMOS technologies as a result of the mobility enhancement in devices. To explore the advantages or the shortcomings of different strained techniques, such as, uniaxial and biaxial strain, further understanding of strained-Si devices related reliability issues is critically important. Therefore, the objective of this work is focused on the reliability characterization of most advanced strained-silicon CMOS devices of 65nm generation and beyond feature size.
In order to investigate the interfacial property of strained-silicon MOSFET's, two measurement methods are developed from our group, the first method is advanced charge-pumping measurement, Incremental Frequency Charge-Pumping (IFCP), from the experimental data, we can study the generated interface traps; the second method is improved novel gated-diode method, Twin-Gated-Diode (T-GD), it can be employed to measure the recombination current and the profiling of interface trap density based on the Shockley-Read-Hall statistics.
In this work, first, basic characteristics of the devices were discussed and by applying hot carrier stress, the electrical reliability of this new generation devices using IFCP method has been evaluated. From the results, we have been able to identify the more enhanced hot carrier degradation in biaxially-strained nMOSFET or pMOSFET was processed a two-dimensional strain in active region of device has a major concern with lattice misfit, comparing to conventional bulk devices and uniaxially-strained nMOSFET or pMOSFET. Therefore, in uniaxially-strained and biaxially-strained nMOSFET or pMOSFET devices, hot carrier degradation is one of the major concerns for developing next generation logic devices.
Then, we followed by studying the temperature dependence hot carrier degradation. The electrical reliability of strained pMOSFET devices using T-GD method has been evaluated. We found that SiGe S/D uniaxial strain has smaller interface traps near the drain junction region during NBTI stress. From the threshold voltage, comparing to conventional bulk devices and SiGe S/D uniaxial strain, we reported that the temperature-dependence hot carrier degradation behavior was enhanced by the SiGe material which occupies the most part of generated interface traps region in strained-Si devices. These results will be helpful towards an understanding of the physical mechanism for local stresses and its correlation to the device degradation. The interface traps distribution provides us important information for the understanding of the device reliabilities of strained-Si devices.
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