Power Reduction for Scan Testing Based on Scan Cell Ordering 降低掃瞄試期間之功率消耗Power Reduction for Scan Testing Based on Scan Cell Ordering
碩士 === 元智大學 === 資訊工程學系 === 94 === Scan-based circuit structure is widely used in circuit test design. The power consumption of a CUT (Circuit Under Test), however, arises during the test procedure. Excessive power consumption during test procedure may increase the cost of product and results in the...
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| Format: | Others |
| Language: | en_US |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/08722003069959744814 |