| Summary: | 碩士 === 國立臺灣科技大學 === 電子工程系 === 93 === As technology scales to the very deep submicron (VDSM) dimensions, the coupling capacitances between adjacent bus wire grow rapidly, and have a significant impact on power consumption and signal integrity issue of whole chip. Thus, it is important to design fault-tolerant buses that dissipate less power and raise reliability without sacrificing performance.
In this paper, we address the problem of using Hamming single error correcting code by simultaneously optimizing wire permutation and spacing. We propose an efficient algorithm that use graph theory for this optimization problem in a polynomial time. Unlike previous study, our approach using in high bandwidth fault-tolerant buses can efficient reduce the coupling capacitances without more additional space.
For our experiments, we used instruction bus traces obtained from 12 SPEC2000 benchmark programs. The results show that our approach can save energy up to 43% for the best case, and 30% for the worst with 20×dmin additional width.
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