Wire Permutation and Spacing for Low Power Fault-Tolerant Bus
碩士 === 國立臺灣科技大學 === 電子工程系 === 93 === As technology scales to the very deep submicron (VDSM) dimensions, the coupling capacitances between adjacent bus wire grow rapidly, and have a significant impact on power consumption and signal integrity issue of whole chip. Thus, it is important to design fault...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/84296012282043985278 |