A design of Phase-Locked Loop for the application in optical transmitter
碩士 === 國立臺灣科技大學 === 電子工程系 === 94 === This thesis describes a design of PLL clock generator for optical transmitter in a standard CMOS process. It can produce multiple-times clocks for a multiplexer which combines the parallel sequences of data at lower rates to generate a single high-speed serial si...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/9z6t2n |