Quick RTL Synthesis for Design Analysis and Verification
碩士 === 國立臺灣大學 === 電機工程學研究所 === 94 === In this thesis, we proposed a quick register transfer level(RTL) front end for design analysis and verification. Our front end consists of three parts: (1) an RTL parser that supports most of the synthesizable Verilog subset and various library formats; (2) an e...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/71303389930343693812 |