Statistical Thermal- and Timing-Constrained Circuit Optimization

• Main Authors: Tsui-Yee Ling, 林翠薏
• Other Authors: Yao-Wen Chang
• Format: Others
• Language: en_US
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/28879910534453839248

碩士 === 國立臺灣大學 === 電機工程學研究所 === 94 === Process Variation has become a crucial challenge on both interconnect delay and reliability of nanometer integrated circuit designs. Furthermore, the dramatic increase of ower consumption and integration density has led to high operating temperature. Temperature, as well as electromigration (EM) and power, also significantly affects the delay and reliability of interconnects. Considering process variation, we present the firrst work to use statistical methods to optimize the circuit area under timing and thermal yield constraints by sizing both wires and gates. We model the problem as a second-order conic program (SOCP) and solve it with the interior-point optimization method. Experimental results show that our statistical algorithm can find solutions that satisfy all constraints and on average improves the circuit areas by respective 44.03%, 33.25%, and 21.74% with 70.0%, 84.1%, and 99.9% yields after wire and gate sizing. Further, the log-log curve of the runtime shows that our empirical time complexity is only about O(N^0.9) for solving SOCPs by the interior-point method, which is sublinear to the circuit size, N. In particular, our empirical time complexity is even better than the previously reported O(N^1.3) bound, showing our efficient implementation.